----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:24:35 04/22/2012 
-- Design Name: 
-- Module Name:    nes_controller - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE, work;
use IEEE.STD_LOGIC_1164.ALL;
use work.game_support.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity nes_controller is
    Port ( clk : in  STD_LOGIC;
				load : out std_logic;
           serial_data : in  STD_LOGIC;
			  direction : out paddle_direction);
end nes_controller;

architecture Behavioral of nes_controller is

	constant latch_modulus : positive := 10;
	signal count : positive range 1 to latch_modulus := 1;
	
	signal button_data_internal : std_logic_vector(7 downto 0) := (others => '0');

begin

	process(clk, count)
	begin
		if rising_edge(clk) then
			if count = 1 then
				count <= count + 1;
				load <= '1';
			else
				load <= '0';
				if count = latch_modulus then
					count <= 1;
				else
					count <= count + 1;
				end if;				
			end if;
		end if;
	end process;
	
	process(clk,count)
	begin
		if rising_edge(clk) then
			if count <= 8 then
				button_data_internal <= button_data_internal(6 downto 0) & serial_data;
			end if;
		end if;
	end process;
	
	with button_data_internal select direction <=
		left when "11111101",
		right when "11111110",
		stay when others;

end Behavioral;

